1. Field of the Invention
This invention relates to computer systems and, more particularly, to integrated bus bridge designs for use in high performance computer systems. The invention also relates to delayed transaction operations supported by a bus bridge.
2. Description of the Related Art
Computer architectures generally include a plurality of devices interconnected by one or more buses. For example, conventional computer systems typically include a CPU coupled through bridge logic to an external main memory. A main memory controller is thus typically incorporated within the bridge logic to generate various control signals for accessing the main memory. An interface to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (PCI) bus, may also be included as a portion of the bridge logic. Examples of devices which can be coupled to the local expansion bus include network interface cards, video accelerators, audio cards, SCSI adapters, telephony cards, etc. An older-style expansion bus may be supported through yet an additional bus interface to provide compatibility with earlier-version expansion bus adapters. Examples of such expansion buses include the Industry Standard Architecture (ISA) bus, also referred to as the AT bus, the Extended Industry Standard Architecture (EISA) bus, and the Microchannel Architecture (MCA) bus. Various devices may be coupled to this second expansion bus, including a fax/modem card, sound card, etc.
The bridge logic can link or interface more than simply the CPU bus, a peripheral bus such as a PCI bus, and the memory bus. In applications that are graphics intensive, a separate peripheral bus optimized for graphics related transfers may be supported by the bridge logic. A popular example of such a bus is the AGP (Advanced Graphics Port) bus. AGP is generally considered a high performance, component level interconnect optimized for three dimensional graphical display applications, and is based on a set of performance extensions or enhancements to PCI. AGP came about, in part, from the increasing demands placed on memory bandwidths for three dimensional renderings. AGP provided an order of magnitude bandwidth improvement for data transfers between a graphics accelerator and system memory. This allowed some of the three dimensional rendering data structures to be effectively shifted into main memory, relieving the costs of incorporating large amounts of memory local to the graphics accelerator or frame buffer.
AGP uses the PCI specification as an operational baseline, yet provides three significant performance extensions or enhancements to that specification. These extensions include a deeply pipelined read and write operation, demultiplexing of address and data on the AGP bus, and ac timing specifications for faster data transfer rates.
Since computer systems were originally developed for business applications including word processing and spreadsheets, among others, the bridge logic within such systems was generally optimized to provide the CPU with relatively good performance with respect to its access to main memory. The bridge logic generally provided relatively poor performance, however, with respect to main memory accesses by other devices residing on peripheral busses, and similarly provided relatively poor performance with respect to data transfers between the CPU and peripheral busses as well as between peripheral devices interconnected through the bridge logic.
Recently, however, computer systems have been increasingly utilized in the processing of various real time applications, including multimedia applications such as video and audio, telephony, and speech recognition. These systems require not only that the CPU have adequate access to the main memory, but also that devices residing on various peripheral busses such as an AGP bus and a PCI bus have fair access to the main memory. Furthermore, it is often important that transactions between the CPU, the AGP bus and the PCI bus be efficiently handled. The bus bridge logic for a modem computer system should accordingly include mechanisms to efficiently prioritize and arbitrate among the varying requests of devices seeking access to main memory and to other system components coupled through the bridge logic.
To optimize efficiency, some bus bridge designs support delayed transaction operations. For example, in systems supporting delayed read operations, when a read cycle to main memory is initiated on a bus such as the PCI bus, the bus bridge detects the cycle and, rather than completing the cycle on the peripheral bus, the bus interface unit terminates or retries the cycle on the PCI bus. This frees the PCI bus to accommodate transactions by other devices. The bus interface unit concurrently requests the data from memory corresponding to the retried read cycle and holds the data in a buffer once it has been retrieved from memory. Ultimately, the PCI master establishing the delayed read operation will reattempt the read operation, at which time the bus interface unit can immediately provide the read data from its buffer. More efficient use of the PCI bus can thereby be attained. Similar delayed transactions may be supported in other devices, such as bus bridge devices. Furthermore, delayed write transactions may also be implemented in a similar manner for non-postable writes.
Normally, when a delayed read is established by a PCI master, the read data is held within the bus bridge until the PCI master reattempts the read operation. If the PCI master does not reattempt the read operation within a given time, the delayed read data is discarded from the bus bridge buffers. Typically, in most PCI compliant systems, the delayed read data is discarded if the PCI master does not reaftempt the read within 2.sup.15 PCI clock cycles.
In systems employing a secondary bus bridge such an ISA bridge that provides an interface between a PCI bus and an ISA bus, inefficiencies can arise if a delayed read from main memory is established by a PCI master at the same time the PCI bus is in the process of being handed over to the ISA bridge to perform a memory read on behalf of an ISA device. When an ISA device must read data from main memory, any pending CPU to PCI transactions pending in the bus bridge must typically be flushed prior to performing the ISA read operation from main memory. Thus, before granting mastership of the PCI bus to the ISA bridge, any pending CPU to PCI transactions are flushed, and subsequently ownership of the PCI bus is granted to the ISA bridge to allow initiation of the read operation on the PCI bus. Unfortunately, if a delayed read operation is established by another PCI master prior to the ISA bridge receiving PCI bus ownership and initiating the read operation, the ISA bridge may be unable to complete the read operation once it has the bus until after the pending delayed read data is discarded. Furthermore, since the PCI master will not be able to access the bus while the ISA device is holding the PCI bus, it also can not re-initiate its read to read the pending delayed read data. As stated previously, the discard time for discarding delayed read data can be quite lengthy. Accordingly, poor performance may result when an ISA device requires frequent read operations to main memory. Similar problems may also be associated with systems supporting delayed write transactions, and in systems having bus bridges which support delayed transactions.